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M59DR032A M59DR032B
32 Mbit (2Mb x16, Dual Bank, Page) Low Voltage Flash Memory
PRELIMINARY DATA
s
SUPPLY VOLTAGE - VDD = VDDQ = 1.65V to 2.2V: for Program, Erase and Read - VPP = 12V: optional Supply Voltage for fast Program and Erase
s
ASYNCHRONOUS PAGE MODE READ
BGA
- Page Width: 4 words - Page Access: 35ns - Random Access: 100ns
s
PROGRAMMING TIME - 10s by Word typical - Double Word Programming Option
TSOP48 (N) 12 x 20mm
FBGA48 (ZB) 8 x 6 solder balls
s
MEMORY BLOCKS - Dual Bank Memory Array: 4 Mbit - 28 Mbit - Parameter Blocks (Top or Bottom location) - Main Blocks Figure 1. Logic Diagram
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DUAL BANK OPERATIONS - Read within one Bank while Program or Erase within the other - No delay between Read and Write operations
VDD VDDQ VPP 21 A0-A20 W E G RP WP M59DR032A M59DR032B 16 DQ0-DQ15
s
BLOCK PROTECTION/UNPROTECTION - All Blocks protected at Power Up - Any combination of Blocks can be protected - WP for Block Locking
s s s s
COMMON FLASH INTERFACE (CFI) 64 bit SECURITY CODE ERASE SUSPEND and RESUME MODES 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION - Defectivity below 1ppm/year
s
VSS
AI02544B
s
ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code, M59DR032A: A0h - Device Code, M59DR032B: A1h
October 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M59DR032A, M59DR032B
Figure 2A. FBGA Connections (Top View)
1 2 3 4 5 6 7 8
A
A13
A11
A8
VPP
WP
A19
A7
A4
B
A14
A10
W
RP
A18
A17
A5
A2
C
A15
A12
A9
DU
A20
A6
A3
A1
D
A16
DQ14
DQ5
DQ11
DQ2
DQ8
E
A0
E
VDDQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
VSS
F
VSS
DQ7
DQ13
DQ4
VDD
DQ10
DQ1
G
AI02532C
Figure 2B. TSOP Connections
A15 A14 A13 A12 A11 A10 A9 A8 NC A20 W RP VPP WP A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 A16 VDDQ VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
Table 1. Signal Names
A0-A20 DQ0-DQ15 E G W RP WP VDD VDDQ VPP VSS NC DU Address Inputs Data Input/Outputs, Command Inputs Chip Enable Output Enable Write Enable Reset/Power Down Write Protect Circuitry Supply Voltage Input/Output Buffers Supply Voltage Optional Supply Voltage for Fast Program & Erase Ground Not Connected Internally Don't use as internally connected
12 13
M59DR032A M59DR032B
37 36
24
25
AI02533B
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M59DR032A, M59DR032B
Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO (3) VDD, VDDQ VPP Parameter Ambient Operating Temperature (2) Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Program Voltage Value -40 to 85 -40 to 125 -55 to 155 -0.5 to VDDQ+0.5 -0.5 to 2.7 -0.5 to 13 Unit C C C V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Depends on range. 3. Minimum Voltage may undershoot to -2V during transition and for less than 20ns.
DESCRIPTION The M59DR032 is a 32 Mbit non-volatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-byWord basis using a 1.65V to 2.2V V DD supply for the circuitry. For Program and Erase operations the necessary high voltages are generated internally. The device supports asynchronous page mode from all the blocks of the memory array. The array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. All blocks are protected against programming and erase at Power Up. Blocks can be unprotected to make changes in the application and then reprotected. Instructions for Read/Reset, Auto Select, Write Configuration Register, Programming, Block Erase, Bank Erase, Erase Suspend, Erase Resume, Block Protect, Block Unprotect, Block Locking, CFI Query, are written to the memory through a Command Interface using standard microprocessor write timings. The device is offered in TSOP48 (12 x 20 mm) and in FBGA48 0.75 mm ball pitch packages. When shipped all bits of the M59DR032 device are at the logical level `1'. Organization The M59DR032 is organized as 2Mb x16 bits. A0A20 are the address lines, DQ0-DQ15 are the Data Input/Output. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs.
Reset RP is used to reset all the memory circuitry and to set the chip in power down mode if this function is enabled by a proper setting of the Configuration Register. Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, DQ6 and DQ2 provide Toggle signals and DQ5 provides error bit to indicate the state of the P/E.C operations. Memory Blocks The device features asymmetrically blocked architecture. M59DR032 has an array of 71 blocks and is divided into two banks A and B, providing Dual Bank operations. While programming or erasing in Bank A, read operations are possible into Bank B or vice versa. The memory also features an erase suspend allowing to read or program in another block within the same bank. Once suspended the erase can be resumed. The Bank Size and Sectorization are summarized in Table 7. Parameter Blocks are located at the top of the memory address space for the M59DR032A, and at the bottom for the M59DR032B. The memory maps are shown in Tables 3, 4, 5 and 6. The Program and Erase operations are managed automatically by the P/E.C. Block protection against Program or Erase provides additional data security. All blocks are protected at Power Up. Instructions are provided to protect or unprotect any block in the application. A second register locks the protection status while WP is low (see Block Locking description). The Reset command does not affect the configuration of unprotected blocks and the Configuration Register status.
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M59DR032A, M59DR032B
Table 3. Bank A, Top Boot Block Address
Size (KWord) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 Address Range 1FF000h-1FFFFFh 1FE000h-1FEFFFh 1FD000h-1FDFFFh 1FC000h-1FCFFFh 1FB000h-1FBFFFh 1FA000h-1FAFFFh 1F9000h-1F9FFFh 1F8000h-1F8FFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 000000h-007FFFh
Table 4. Bank B, Top Boot Block Address
Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 130000h-137FFFh
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Table 5. Bank B, Bottom Boot Block Address
Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 1F8000h-1FFFFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh
Table 6. Bank A, Bottom Boot Block Address
Size (KWord) 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Address Range 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 007000h-007FFFh 006000h-006FFFh 005000h-005FFFh 004000h-004FFFh 003000h-003FFFh 002000h-002FFFh 001000h-001FFFh 000000h-000FFFh
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M59DR032A, M59DR032B
Table 7. Bank Size and Sectorization
Bank Size Bank A Bank B 4 Mbit 28 Mbit Parameter Blocks 8 blocks of 4 KWord Main Blocks 7 blocks of 32 KWord 56 blocks of 32 KWord
SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A20). The address inputs for the memory array are latched during a write operation on the falling edge of Chip Enable E or Write Enable W, whichever occurs last. Data Input/Output (DQ0-DQ15). The Input is data to be programmed in the memory array or a command to be written to the Command Interface (C.I.) Both input data and commands are latched on the rising edge of Write Enable W. The Ouput is data from the Memory Array, the Common Flash Interface, the Electronic Signature Manufacturer or Device codes, the Block Protection status, the Configuration Register status or the Status Register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5. The data bus is high impedance when the chip is deselected, Output Enable G is at VIH, or RP is at V IL. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E at VIH deselects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at V IL. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. When G is at VIH the outputs are High impedance. Write Enable (W). This input controls writing to the Command Register and Data latches. Data are latched on the rising edge of W. Write Protect (WP). This input gives an additional hardware protection level against program or erase when pulled at VIL, as described in the Block Lock instruction description. Reset/Power Down Input (RP). The RP input provides hardware reset of the memory (without affecting the Configuration Register status), and/ or Power Down functions, depending on the Configuration Register status. Reset/Power Down of the memory is achieved by pulling RP to V IL for at least tPLPH. When the reset pulse is given, if the memory is in Read, Erase Suspend Read or Standby, it will output new valid data in tPHQ7V1 after the rising edge of RP. If the memory is in Erase or Program modes, the operation will be aborted
and the reset recovery will take a maximum ot tPLQ7V. The memory will recover from Power Down (when enabled) in tPHQ7V2 after the rising edge of RP. See Tables 25, 26 and Figure 9. VDD and VDDQ Supply Voltage (1.65V to 2.2V). The main power supply for all operations (Read, Program and Erase). V DD and VDDQ must be at the same voltage. VPP Programming Voltage (11.4V to 12.6V). Used to provide high voltage for fast factory programming. High voltage on VPP pin is required to use the Double Word Program instruction. It is also possible to perform word program or erase instructions with VPP pin grounded. VSS Ground. VSS is the reference for all the voltage measurements. DEVICE OPERATIONS The following operations can be performed using the appropriate bus cycles: Read Array (Random, and Page Modes), Write command, Output Disable, Standby, Reset/Power Down and Block Locking. See Table 8. Read. Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register, the CFI, the Block Protection Status or the Configuration Register status. Read operation of the memory array is performed in asynchronous page mode, that provides fast access time. Data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by A0-A1 address inputs. Read operations of the Electronic Signature, the Status Register, the CFI, the Block Protection Status, the Configuration Register status and the Security Code are performed as single asyncronous read cycles (Random Read). Both Chip Enable E and Output Enable G must be at VIL in order to read the output of the memory. Write. Write operations are used to give Instruction Commands to the memory or to latch Input Data to be programmed. A write operation is initiated when Chip Enable E and Write Enable W are at V IL with Output Enable G at VIH. Addresses are latched on the falling edge of W or E whichever occurs last. Commands and Input Data are latched on the rising edge of W or E whichever occurs first. Noise pulses of less than 5ns typical on E, W and G signals do not start a write cycle.
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Table 8. User Bus Operations (1)
Operation Write Output Disable Standby Reset / Power Down Block Locking
Note: 1. X = Don't care.
E VIL VIL VIH X VIL
G VIH VIH X X X
W VIL VIH X X X
RP VIH VIH VIH VIL VIH
WP VIH VIH VIH VIH VIL
DQ15-DQ0 Data Input Hi-Z Hi-Z Hi-Z X
Table 9. Read Electronic Signature (AS and Read CFI instructions)
Code Manufacturer Code M59DR032A Device Code M59DR032B VIL VIL VIH VIH VIL 0 Don't Care 00h A1h Device E VIL VIL G VIL VIL W VIH VIH A0 VIL VIH A1 VIL VIL A7-A2 0 0 Other DQ15-DQ8 Addresses Don't Care Don't Care 00h 00h DQ7-DQ0 20h A0h
Table 10. Read Block Protection (AS and Read CFI instructions)
Block Status Protected Block Unprotected Block Locked Block E VIL VIL VIL G VIL VIL VIL W VIH VIH VIH A0 VIL VIL VIL A1 VIH VIH VIH A20-A12 Block Address Block Address Block Address A7-A2 0 0 0 Other Addresses Don't Care Don't Care Don't Care DQ0 1 0 X DQ1 0 0 1 DQ15-DQ2 0000h 0000h 0000h
Table 11. Read Configuration Register (AS and Read CFI instructions)
RP Function Reset Reset/Power Down E VIL VIL G VIL VIL W VIH VIH A0 VIH VIH A1 VIH VIH A7-A2 0 0 Other Addresses Don't Care Don't Care DQ10 0 1 DQ9-DQ0 DQ15-DQ11 Don't Care Don't Care
Dual Bank Operations. The Dual Bank allows to read data from one bank of memory while a program or erase operation is in progress in the other bank of the memory. Read and Write cycles can be initiated for simultaneous operations in different banks without any delay. Status Register during Program or Erase must be monitored using an address within the bank being modified. Output Disable. The data outputs are high impedance when the Output Enable G is at VIH with Write Enable W at VIH. Standby. The memory is in standby when Chip Enable E is at VIH and the P/E.C. is idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs.
Automatic Standby. When in Read mode, after 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while outputs still drive the bus. Power Down. The memory is in Power Down when the Configuration Register is set for Power Down and RP is at VIL. The power consumption is reduced to the Power Down level, and Outputs are in high impedance, independent of the Chip Enable E, Output Enable G or Write Enable W inputs. Block Locking. Any combination of blocks can be temporarily protected against Program or Erase by setting the lock register and pulling WP to VIL (see Block Lock instruction).
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INSTRUCTIONS AND COMMANDS Seventeen instructions are defined (see Table 14A), and the internal P/E.C. automatically handles all timing and verification of the Program and Erase operations. The Status Register Data Polling, Toggle, Error bits can be read at any time, during programming or erase, to monitor the progress of the operation. Instructions, made up of one or more commands written in cycles, can be given to the Program/ Erase Controller through a Command Interface (C.I.). The C.I. latches commands written to the memory. Commands are made of address and data sequences. Two Coded Cycles unlock the Command Interface. They are followed by an input command or a confirmation command. The Coded Sequence consists of writing the data AAh at the address 555h during the first cycle and the data 55h at the address 2AAh during the second cycle. Instructions are composed of up to six cycles. The first two cycles input a Coded Sequence to the Command Interface which is common to all instructions (see Table 14A). The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data, Electronic Signature, Block Protection, Configuration Register Status or CFI Query for Read operations. In order to give additional data protection, the instructions for Block Erase and Bank Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For a Double Word Programming instruction, the fourth and fifth command cycles input the address and data to be programmed. For a Block Erase and Bank Erase instructions, the fourth and fifth cycles input a further Coded Sequence before the Erase confirm command on the sixth cycle. Any combination of blocks of the same memory bank can be erased. Erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. When power is first applied the command interface is reset to Read Array. Command sequencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array. The increased number of cycles has been chosen to ensure maximum data security. Read/Reset (RD) Instruction. The Read/Reset instruction consists of one write cycle giving the command F0h. It can be optionally preceded by the two Coded Cycles. Subsequent read operations will read the memory array addressed and output the data read. CFI Query (RCFI) Instruction. Common Flash Interface Query mode is entered writing 98h at address 55h. The CFI data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. Tables 15, 16, 17 and 18 show the addresses used to retrieve each data. The CFI data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at address 80h. This area can be accessed only in read mode by the final user and there are no ways of changing the code after it has been written by ST. Write a read instruction (RD) to return to Read mode.
Table 12. Commands
Hex Code 00h 10h 20h 30h 40h Bypass Reset Bank Erase Confirm Unlock Bypass Block Erase Resume/Confirm Double Word Program Block Protect, or Block Unprotect, or Block Lock, or Write Configuration Register Set-up Erase Read Electronic Signature, or Block Protection Status, or Configuration Register Status CFI Query Program Erase Suspend Read Array/Reset Command
60h
80h 90h 98h A0h B0h F0h
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M59DR032A, M59DR032B
Auto Select (AS) Instruction. This instruction uses two Coded Cycles followed by one write cycle giving the command 90h to address 555h for command set-up. A subsequent read will output the Manufacturer or the Device Code (Electronic Signature), the Block Protection status or the Configuration Register status depending on the levels of A0 and A1 (see Tables 9, 10 and 11). A7-A2 must be at V IL, while other address input are ignored. The bank address is don't care for this instruction. The Electronic Signature can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of M59DR032. The Manufacturer Code is output when the address lines A0 and A1 are at V IL, the Device Code is output when A0 is at VIH with A1 at VIL. The codes are output on DQ0-DQ7 with DQ8DQ15 at 00h. The AS instruction also allows the access to the Block Protection Status. After giving the AS instruction, A0 is set to VIL with A1 at VIH, while A12-A20 define the address of the block to be verified. A read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected. The AS Instruction finally allows the access to the Configuration Register status if both A0 and A1 are set to VIH. If DQ10 is '0' only the Reset function is active as RP is set to VIL (default at power-up). If DQ10 is '1' both the Reset and the Power Down functions will be achieved by pulling RP to VIL. The other bits of the Configuration Register are reserved and must be ignored. A reset command puts the device in read array mode. Write Configuration Register (CR) Instruction. This instruction uses two Coded Cycles followed by one write cycle giving the command 60h to address 555h. A further write cycle giving the command 03h writes the contents of address bits A0-A15 to the 16 bits configuration register. Bits written by inputs A0-A9 and A11-A15 are reserved for future use. Address input A10 defines the status of the Reset/Power Down functions. It must be set to V IL to enable only the Reset function and to VIH to enable also the Power Down function. At Power Up all the Configuration Register bits are reset to '0'. Enter Bypass Mode (EBY) Instruction. This instruction uses the two Coded cycles followed by one write cycle giving the command 20h to address 555h for mode set-up. Once in Bypass mode, the device will accept the Exit Bypass (XBY) and Program or Double Word Program in Bypass mode (PGBY, DPGBY) commands. The Bypass mode allows to reduce the overall programming time when large memory arrays need to be programmed. Exit Bypass Mode (XBY) Instruction. This instruction uses two write cycles. The first inputs to the memory the command 90h and the second inputs the Exit Bypass mode confirm (00h). After the XBY instruction, the device resets to Read Memory Array mode. Program in Bypass Mode (PGBY) Instruction. This instruction uses two write cycles. The Program command A0h is written to any Address on the first cycle and the second write cycle latches the Address on the falling edge of W or E and the Data to be written on the rising edge and starts the P/E.C. Read operations within the same bank output the Status Register bits after the programming has started. Memory programming is made only by writing '0' in place of '1'. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Program (PG) Instruction. This instruction uses four write cycles. The Program command A0h is written to address 555h on the third cycle after two Coded Cycles. A fourth write operation latches the Address and the Data to be written and starts the P/E.C. Read operations within the same bank output the Status Register bits after the programming has started. Memory programming is made only by writing '0' in place of '1'. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Programming at an address not in blocks being erased is also possible during erase suspend. Double Word Program (DPG) Instruction. This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel. High voltage (11.4V to 12.6V) on VPP pin is required. This instruction uses five write cycles. The double word program command 40h is written to address 555h on the third cycle after two Coded Cycles. A fourth write cycle latches the address and data to be written to the first location. A fifth write cycle latches the new data to be written to the second location and starts the P/E.C.. Note that the two locations must have the same address except for the address bit A0. The Double Word Program can be executed in Bypass mode (DPGBY) to skip the two coded cycles at the beginning of each command.
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Table 13. Protection States (1)
Current State (2) (WP, DQ1, DQ0) 100 101 110 111 000 001 011 Program/Erase Allowed yes no yes no yes no no Next State After Event (3) Protect 101 101 111 111 001 001 011 Unprotect 100 100 110 110 000 000 011 Lock 111 111 111 111 011 011 011 WP transition 000 001 011 011 100 101 111 or 110 (4)
Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status. 2. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Autoselect instruction with A1 = VIH and A0 = VIL. 3. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP has changed its logic value. 4. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
Block Protect (BP), Block Unprotect (BU), Block Lock (BL) Instructions. All blocks are protected at power-up. Each block of the array has two levels of protection against program or erase operation. The first level is set by the Block Protect instruction; a protected block cannot be programmed or erased until a Block Unprotect instruction is given for that block. A second level of protection is set by the Block Lock instruction, and requires the use of the WP pin, according to the following scheme: - when WP is at V IH, the Lock status is overridden and all blocks can be protected or unprotected; - when WP is at V IL, Lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. Blocks that are not locked can still change their protection status, and program or erase accordingly; - the lock status is cleared for all blocks at power up; once a block has been locked state can be cleared only with a reset command. The protection and lock status can be monitored for each block using the Autoselect (AS) instruction. Protected blocks will output a `1' on DQ0 and locked blocks will output a `1' on DQ1. Refer to Table 13 for a list of the protection states. Block Erase (BE) Instruction. This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address 555h on third cycle after the two Coded cycles. The Block Erase Confirm command 30h is similarly written on the sixth cycle after another two Coded cycles and an address within the block to be erased is given and latched into the memory.
Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further Coded cycles. All blocks must belong to the same bank of memory; if a new block belonging to the other bank is given, the operation is aborted. The erase will start after an erase timeout period of 100s. Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the internal timer can be monitored through the level of DQ3, if DQ3 is '0' the Block Erase Command has been given and the timeout is running, if DQ3 is '1', the timeout has expired and the P/E.C. is erasing the Block(s). If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as the P/E.C. will do this automatically before erasing to FFh. Read operations within the same bank, after the sixth rising edge of W or E, output the status register bits. During the execution of the erase by the P/E.C., the memory accepts only the Erase Suspend ES instruction; the Read/Reset RD instruction is accepted during the 100s time-out period. Data Polling bit DQ7 returns '0' while the erasure is in progress and '1' when it has completed. The Toggle bit DQ6 toggles during the erase operation, and stops when erase is completed. After completion the Status Register bit DQ5 returns '1' if there has been an erase failure. In such a situation, the Toggle bit DQ2 can be used to determine which block is not correctly erased. In the case of erase failure, a Read/Reset RD instruction is necessary in order to reset the P/E.C.
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M59DR032A, M59DR032B
Bank Erase (BKE) Instruction. This instruction uses six write cycles and is used to erase all the blocks belonging to the selected bank. The Erase Set-up command 80h is written to address 555h on the third cycle after the two Coded cycles. The Bank Erase Confirm command 10h is similarly written on the sixth cycle after another two Coded cycles at an address within the selected bank. If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing it to FFh. Read operations within the same bank after the sixth rising edge of W or E output the Status Register bits. During the execution of the erase by the P/E.C., Data Polling bit DQ7 returns '0', then '1' on completion. The Toggle bit DQ6 toggles during erase operation and stops when erase is completed. After completion the Status Register bit DQ5 returns '1' if there has been an Erase Failure. Erase Suspend (ES) Instruction. In a dual bank memory the Erase Suspend instruction is used to read data within the bank where erase is in progress. It is also possible to program data in blocks not being erased. The Erase Suspend instruction consists of writing the command B0h without any specific address. No Coded Cycles are required. Erase suspend is accepted only during the Block Erase instruction execution. The Toggle bit DQ6 stops toggling when the P/E.C. is suspended within 15s after the Erase Suspend (ES) command has been written. The device will then automatically be set to Read Memory Array mode. When erase is suspended, a Read from blocks being erased will output DQ2 toggling and DQ6 at '1'. A Read from a block not being erased returns valid data. During suspension the memory will respond only to the Erase Resume ER and the Program PG instructions. A Program operation can be initiated during erase suspend in one of the blocks not being erased. It will result in DQ6 toggling when the data is being programmed. Erase Resume (ER) Instruction. If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at an address within the bank being erased and without any Coded Cycle.
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M59DR032A, M59DR032B
Table 14A. Instructions (1,2)
Mne. Instr. Cyc. 1+ RD (4) Read/Reset Memory Array 3+ Data Addr. RCFI CFI Query 1+ Data Addr. AS
(4)
1st Cyc. Addr. (3) Data Addr. X
2nd Cyc.
3rd Cyc.
4th Cyc.
5th Cyc.
6th Cyc.
Read Memory Array until a new write cycle is initiated. F0h 555h AAh 55h Read CFI data until a new write cycle is initiated. 98h 555h AAh 555h AAh 555h AAh 555h AAh 555h AAh X 90h X A0h X 40h 555h AAh 555h AAh 2AAh 55h 2AAh 55h 2AAh 55h 2AAh 55h 2AAh 55h X 00h Program Address Read Data Polling or Toggle Bit until Program Program completes. Data Program Program Address 1 Address 2 Note 6, 7 Program Data 1 2AAh 55h 2AAh 55h Program Data 2 555h 60h 555h 60h Block Address 01h Block Address D0h 555h 90h 555h 60h 555h A0h 555h 40h 555h 20h Read electronic Signature or Block Protection or Configuration Register Status until a new cycle is initiated. Configuration Data 03h Program Address Read Data Polling or Toggle Bit until Program Program completes. Data Program Program Address 1 Address 2 Note 6, 7 Program Data 1 Program Data 2 2AAh 55h 555h F0h Read Memory Array until a new write cycle is initiated.
Auto Select
3+ Data Addr. 4 Data Addr.
CR
Configuration Register Write
PG
Program
4 Data Addr.
DPG
Double Word Program
5 Data
EBY
Enter Bypass Mode Exit Bypass Mode
Addr. 3 Data Addr. 2 Data Addr.
XBY
PGBY
Program in Bypass Mode
2 Data Addr. 3 Data Addr.
Double Word DPGBY Program in Bypass Mode
BP
Block Protect
4 Data Addr.
BU
Block Unprotect
1 Data
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M59DR032A, M59DR032B
Table 14B. Instructions (1,2)
Mne. Instr. Cyc. Addr. BL Block Lock 4 Data Addr. BE Block Erase 6+ Data Addr. BKE Bank Erase 6 Data ES Erase Suspend 1 Addr. (3) Data Addr. ER Erase Resume 1 Data
Note: 1. 2. 3. 4.
1st Cyc. 555h AAh 555h AAh 555h AAh X B0h Bank Address 30h
2nd Cyc. 2AAh 55h 2AAh 55h 2AAh 55h
3rd Cyc. 555h 60h 555h 80h 555h 80h
4th Cyc. Block Address 2Fh 555h AAh 555h AAh
5th Cyc.
6th Cyc.
2AAh 55h 2AAh 55h
Block Address 30h Bank Address 10h
Read until Toggle stops, then read all the data needed from any Blocks not being erased then Resume Erase.
Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time
Commands not interpreted in this table will default to read array mode. For Coded cycles address inputs A11-A20 are don't care. X = Don't Care. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the command cycles. 5. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased. 6. Program Address 1 and Program Address 2 must be consecutive addresses differing only for address bit A0. 7. High voltage on VPP (11.4V to 12.6V) is required for the proper execution of the Double Word Program instruction.
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M59DR032A, M59DR032B
Table 15. Query Structure Overview
Offset 00h 10h 1Bh 27h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional)
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailled in Tables 16, 17 and 18. Query data are always presented on the lowest order data outputs.
Table 16. CFI Query Identification String
Offset 00h 01h 02h-0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0020h 00A1h - bottom 00A0h - top reserved 0051h 0052h 0059h 0002h 0000h offset = P = 0040h Address for Primary Algorithm extended Query table 0000h 0000h 0000h value = A = 0000h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported (note: 0000h means none exists) Address for Alternate Algorithm extended Query table note: 0000h means none exists Manufacturer Code Device Code Reserved Query Unique ASCII String "QRY" Query Unique ASCII String "QRY" Query Unique ASCII String "QRY" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Description
Note: Query data are always presented on the lowest - order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'.
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M59DR032A, M59DR032B
Table 17. CFI Query System Interface Information
Offset 1Bh Data 0017h Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Note: This value must be 0000h if no VPP pin is present VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Note: This value must be 0000h if no VPP pin is present Typical timeout per single byte/word program (multi-byte program count = 1), 2n s (if supported; 0000h = not supported) Typical timeout for maximum-size multi-byte program or page write, 2n s (if supported; 0000h = not supported) Typical timeout per individual block erase, 2n ms (if supported; 0000h = not supported) Typical timeout for full chip erase, 2n ms (if supported; 0000h = not supported) Maximum timeout for byte/word program, 2n times typical (offset 1Fh) (0000h = not supported) Maximum timeout for multi-byte program or page write, 2n times typical (offset 20h) (0000h = not supported) Maximum timeout per individual block erase, 2n times typical (offset 21h) (0000h = not supported) Maximum timeout for chip erase, 2n times typical (offset 22h) (0000h = not supported)
1Ch
0022h
1Dh
0000h
1Eh
00C0h
1Fh 20h 21h 22h 23h 24h 25h 26h
0004h 0000h 000Ah 0000h 0004h 0000h 0004h 0000h
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M59DR032A, M59DR032B
Table 18. Device Geometry Definition
Offset Word Mode 27h 28h 29h 2Ah 2Bh 2Ch Data 0016h 0001h 0000h 0000h 0000h 0002h Device Size = 2n in number of bytes Flash Device Interface Code description: Asynchronous x16 Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions within device bit 7 to 0 = x = number of Erase Block Regions Note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk." 2. x specifies the number of regions within the device containing one or more contiguous Erase Blocks of the same size. For example, a 128KB device (1Mb) having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is considered to have 5 Erase Block Regions. Even though two regions both contain 16KB blocks, the fact that they are not contiguous means they are separate Erase Block Regions. 3. By definition, symmetrically block devices have only one blocking region. M59DR032A 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h M59DR032B 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h M59DR032A Erase Block Region Information 003Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h M59DR032B 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes in size. The value z = 0 is used for 128 byte block size. e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K bit 15 to 0 = y, where y+1 = Number of Erase Blocks of identical size within the Erase Block Region: e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number] y = 0 means no blocking (# blocks = y+1 = "1 block") Note: y = 0 value must be used with number of block regions of one as indicated by (x) = 0 Description
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M59DR032A, M59DR032B
Table 19. Status Register Bits (1)
DQ Name Logic Level '1' '0' 7 Data Polling DQ DQ '-1-0-1-0-1-0-1-' DQ 6 Toggle Bit '-1-1-1-1-1-1-1-' Definition Erase Complete or erase block in Erase Suspend. Erase On-going Program Complete or data of non erase block during Erase Suspend. Program On-going (2) Erase or Program On-going Program Complete Erase Complete or Erase Suspend on currently addressed block Program or Erase Error Program or Erase On-going Successive reads output complementary data on DQ6 while Programming or Erase operations are on-going. DQ6 remains at constant level when P/E.C. operations are completed or Erase Suspend is acknowledged. This bit is set to '1' in the case of Programming or Erase failure. Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success. Note
'1' 5 4 Error Bit '0' Reserved '1' 3 Erase Time Bit '0'
Erase Timeout Period Expired
P/E.C. Erase operation has started. Only possible command entry is Erase Suspend (ES) An additional block to be erased in parallel can be entered to the P/E.C:
Erase Timeout Period On-going Erase Suspend read in the Erase Suspended Block. Erase Error due to the currently addressed block (when DQ5 = '1'). Program on-going or Erase Complete. Erase Suspend read on non Erase Suspend block.
'-1-0-1-0-1-0-1-' 2 Toggle Bit 1 DQ 1 0 Reserved Reserved
Indicates the erase status and allows to identify the erased block.
Note: 1. Logic level '1' is High, '0' is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations. 2. In case of double word program DQ7 refers to the last word input.
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M59DR032A, M59DR032B
Table 20. Polling and Toggle Bits
Mode Program Erase Erase Suspend Read (in Erase Suspend block) Erase Suspend Read (outside Erase Suspend block) Erase Suspend Program DQ7 DQ7 0 DQ6 Toggle Toggle DQ2 1 N/A
1
1
Toggle
DQ7
DQ6
DQ2
DQ7
Toggle
1
STATUS REGISTER BITS P/E.C. status is indicated during execution by Data Polling on DQ7, detection of Toggle on DQ6 and DQ2, or Error on DQ5 bits. Any read attempt within the Bank being modified and during Program or Erase command execution will automatically output these five Status Register bits. The P/E.C. automatically sets bits DQ2, DQ5, DQ6 and DQ7. Other bits (DQ0, DQ1 and DQ4) are reserved for future use and should be masked (see Tables 19 and 20). Read attemps within the bank not being modified will output array data. Data Polling Bit (DQ7). When Programming operations are in progress, this bit outputs the complement of the bit being programmed on DQ7. In case of a double word program operation, the complement is done on DQ7 of the last word written to the command interface, i.e. the data written in the fifth cycle. During Erase operation, it outputs a '0'. After completion of the operation, DQ7 will output the bit last programmed or a '1' after erasing. Data Polling is valid and only effective during P/E.C. operation, that is after the fourth W pulse for programming or after the sixth W pulse for erase. It must be performed at the address being programmed or at an address within the block being erased. See Figure 12 for the Data Polling flowchart and Figure 10 for the Data Polling waveforms. DQ7 will also flag the Erase Suspend mode by switching from '0' to '1' at the start of the Erase Suspend. In order to monitor DQ7 in the Erase Suspend mode an address within a block being erased must be provided. For a Read Operation in
Suspend mode, DQ7 will output '1' if the read is attempted on a block being erased and the data value on other blocks. During Program operation in Erase Suspend Mode, DQ7 will have the same behaviour as in the normal program execution outside of the suspend mode. Toggle Bit (DQ6). When Programming or Erasing operations are in progress, successive attempts to read DQ6 will output complementary data. DQ6 will toggle following toggling of either G, or E when G is at VIL. The operation is completed when two successive reads yield the same output data. The next read will output the bit last programmed or a '1' after erasing. The toggle bit DQ6 is valid only during P/E.C. operations, that is after the fourth W pulse for programming or after the sixth W pulse for Erase. DQ6 will be set to '1' if a Read operation is attempted on an Erase Suspend block. When erase is suspended DQ6 will toggle during programming operations in a block different from the block in Erase Suspend. Either E or G toggling will cause DQ6 to toggle. See Figure 13 for Toggle Bit flowchart and Figure 11 for Toggle Bit waveforms. Toggle Bit (DQ2). This toggle bit, together with DQ6, can be used to determine the device status during the Erase operations. During Erase Suspend a read from a block being erased will cause DQ2 to toggle. A read from a block not being erased will output data. DQ2 will be set to '1' during program operation and to `0' in Erase operation. After erase completion and if the error bit DQ5 is set to '1', DQ2 will toggle if the faulty block is addressed. Error Bit (DQ5). This bit is set to '1' by the P/E.C. when there is a failure of programming or block erase, that results in invalid data in the memory block. In case of an error in block erase or program, the block in which the error occurred or to which the programmed data belongs, must be discarded. Other Blocks may still be used. The error bit resets after a Read/Reset (RD) instruction. In case of success of Program or Erase, the error bit will be set to '0'. Erase Timer Bit (DQ3). This bit is set to `0' by the P/E.C. when the last block Erase command has been entered to the Command Interface and it is awaiting the Erase start. When the erase timeout period is finished, DQ3 returns to `1', in the range of 80s to 120s.
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M59DR032A, M59DR032B
Table 21. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70C; VDD = V DDQ = 1.65V to 2.2V, VPP = VDD unless otherwise specified)
M59DR032 Parameter Min Parameter Block (4 KWord) Erase (Preprogrammed) Main Block (32 KWord) Erase (Preprogrammed) Bank Erase (Preprogrammed, Bank A) Bank Erase (Preprogrammed, Bank B) Chip Program (2) Chip Program (DPG, VPP = 12V) (2) Word Program Program/Erase Cycles (per Block) 100,000 200 Max (1) 2.5 10 Typ 0.15 1 2 10 20 10 10 10 Typical after 100k W/E Cycles 0.4 3 6 30 25 Unit
sec sec sec sec sec sec s cycles
Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or erase should perform significantly better. 2. Excludes the time needed to execute the sequence for program instruction.
POWER SUPPLY Power Down The memory provides Reset/Power Down control input RP. The Power Down function can be activated only if the relevant Configuration Register bit is set to '1'. In this case, when the RP signal is pulled at V SS the supply current drops to typically ICC2 (see Table 22), the memory is deselected and the outputs are in high impedance.If RP is pulled to VSS during a Program or Erase operation, this operation is aborted in tPLQ7V and the memory content is no longer valid (see Reset/Power Down input description).
Power Up The memory Command Interface is reset on Power Up to Read Array. Either E or W must be tied to VIH during Power Up to allow maximum security and the possibility to write a command on the first rising edge of W. Supply Rails Normal precautions must be taken for supply voltage decoupling; each device in a system should have the V DD rails decoupled with a 0.1F capacitor close to the VDD, VDDQ and VSS pins. The PCB trace widths should be sufficient to carry the required VDD program and erase currents.
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M59DR032A, M59DR032B
Table 22. DC Characteristics (TA = 0 to 70C or -40 to 85C; VDD = VDDQ = 1.65V to 2.2V)
Symbol ILI ILO ICC1 ICC2 ICC3 ICC4
(1)
Parameter Input Leakage Current Output Leakage Current Supply Current (Read Mode) Supply Current (Power Down) Supply Current (Standby) Supply Current (Program or Erase) Supply Current (Dual Bank) VPP Supply Current (Program or Erase) VPP Supply Current (Standby or Read) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage CMOS VPP Supply Voltage (Program or Erase)
Test Condition 0V VIN VDD 0V VOUT VDD E = VIL, G = VIH, f = 6MHz RP = VSS 0.2V E = VDD 0.2V Word Program, Block Erase in progress Program/Erase in progress in one Bank, Read in the other Bank VPP = 12V 0.6V VPP VCC VPP = 12V 0.6V
Min
Typ
Max 1 5
Unit A A mA A A mA mA mA A A V V V V
10 2 15 10 20 5 0.2 100 -0.5 VDDQ -0.4
20 10 50 20 40 10 5 400 0.4 VDDQ + 0.4 0.1
ICC5 (1) IPP1 IPP2 VIL VIH VOL VOH VPP (2,3)
IOL = 100A IOH = -100A VDDQ -0.1 -0.4 Double Word Program 11.4
VDD + 0.4 12.6
V V
Note: 1. Sampled only, not 100% tested. 2. VPP may be connected to 12V power supply for a total of less than 100 hrs. 3. For standard program/erase operation VPP is don't care.
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M59DR032A, M59DR032B
Table 23. Capacitance (1) (TA = 25 C, f = 1 MHz)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested.
Table 24. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 4ns 0 to VDDQ VDDQ/2
Figure 4. AC Testing Load Circuit
VDDQ / 2
1N914
3.3k
Figure 3. Testing Input/Output Waveforms
DEVICE UNDER TEST CL = 30pF VDDQ/2 0V
AI02315
OUT
VDDQ
CL includes JIG capacitance
AI02316
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M59DR032A, M59DR032B
Table 25. Read AC Characteristics (TA = 0 to 70C or -40 to 85C; VDD = VDDQ = 1.65V to 2.2V)
M59DR032 Symbol Alt Parameter Test Condition Min tAVAV tAVQV tAVQV1 tELQX (1) tELQV (2) tGLQX (1) tGLQV (2) tEHQX tEHQZ (1) tGHQX tGHQZ (1) tAXQX tPHQ7V1 tPHQ7V2 tPLQ7V tPLPH tRP tRC tACC tPAGE tLZ tCE tOLZ tOE tOH tHZ tOH tDF tOH Address Valid to Next Address Valid Address Valid to Output Valid (Random) Address Valid to Output Valid (Page) Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Transition Output Enable High to Output Hi-Z Address Transition to Output Transition RP High to Data Valid (Read Mode) RP High to Data Valid (Power Down enabled) RP Low to Reset Complete During Program/Erase RP Pulse Width 100 100 E = VIL, G = VIL E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL G = VIL E = VIL E = VIL E = VIL, G = VIL 0 150 50 0 25 0 150 50 15 0 25 0 35 0 25 0 35 0 100 0 35 100 100 35 0 120 100 Max Min 120 120 45 120 Max ns ns ns ns ns ns ns ns ns ns ns ns ns s s ns Unit
Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to t ELQV - tGLQV after the falling edge of E without increasing tELQV .
22/38
tAVAV VALID tAVQV tELQV tAXQX
Figure 5. Random Read AC Waveforms
A0-A20
E tEHQZ tELQX tEHQX
G tGLQV tGLQX VALID tGHQX tGHQZ
DQ0-DQ15
AI02624
M59DR032A, M59DR032B
Note: Write Enable (W) = High.
23/38
24/38
VALID VALID tELQV VALID VALID VALID tGLQV tAVQV tGHQX tEHQZ tAVQV1 VALID VALID VALID tEHQX VALID tGHQZ
AI02538
M59DR032A, M59DR032B
Figure 6. Page Read AC Waveforms
A2-A20
A0-A1
E
G
DQ0-DQ15
M59DR032A, M59DR032B
Table 26. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70 C or -40 to 85 C; VDD = VDDQ = 1.65V to 2.2V)
M59DR032 Symbol Alt Parameter Min tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tVDHEL tWHGL tPLQ7V tVCS tOEH tWC tCS tWP tDS tDH tCH tWPH tAS tAH Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low VDD High to Chip Enable Low Write Enable High to Output Enable Low RP Low to Reset Complete During Program/Erase 100 0 50 50 0 0 30 0 50 0 50 30 15 100 Max Min 120 0 50 50 0 0 30 0 50 0 50 30 15 120 Max ns ns ns ns ns ns ns ns ns ns s ns s Unit
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M59DR032A, M59DR032B
Table 27. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70 C or -40 to 85 C; VDD = VDDQ = 1.65V to 2.2V)
M59DR032 Symbol Alt Parameter Min tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tVDHWL tEHGL tPLQ7V tVCS tOEH tWC tWS tCP tDS tDH tWH tCPH tAS tAH Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low VDD High to Write Enable Low Chip Enable High to Output Enable Low RP Low to Reset Complete During Program/Erase 100 0 50 50 0 0 30 0 50 0 50 30 15 100 Max Min 120 0 50 50 0 0 30 0 50 0 50 30 15 120 Max ns ns ns ns ns ns ns ns ns ns s ns s Unit
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M59DR032A, M59DR032B
Figure 7. Write AC Waveforms, W Controlled
tAVAV A0-A20 VALID tWLAX tAVWL E tELWL G tGHWL W tWHWL tDVWH DQ0-DQ15 VALID tWHDX tWLWH tWHGL tWHEH
VDD tVDHEL
AI02539
Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
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M59DR032A, M59DR032B
Figure 8. Write AC Waveforms, E Controlled
tAVAV A0-A20 VALID tELAX tAVEL W tWLEL G tGHEL E tEHEL tDVEH DQ0-DQ15 VALID tEHDX tELEH tEHGL tEHWH
VDD tVDHWL
AI02540
Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.
28/38
M59DR032A, M59DR032B
Table 28. Data Polling and Toggle Bits AC Characteristics (1) (TA = 0 to 70 C or -40 to 85 C; VDD = VDDQ = 1.65V to 2.2V)
M59DR032 Symbol Parameter Min Write Enable High to DQ7 Valid (Program, W Controlled) tWHQ7V Write Enable High to DQ7 Valid (Block Erase, W Controlled) Chip Enable High to DQ7 Valid (Program, E Controlled) tEHQ7V tQ7VQV tWHQV Chip Enable High to DQ7 Valid (Block Erase, E Controlled) Q7 Valid to Output Valid (Data Polling) Write Enable High to Output Valid (Program) Write Enable High to Output Valid (Block Erase) Chip Enable High to Output Valid (Program) tEHQV Chip Enable High to Output Valid (Block Erase) 10 1.0 10 1.0 10 1.0 10 1.0 Max 200 10 200 10 0 200 10 200 10 s sec s sec ns s sec s sec Unit
Note: 1. All other timings are defined in Read AC Characteristics table.
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M59DR032A, M59DR032B
Figure 9. Read and Write AC Characteristics, RP Related
VALID
PROGRAM / ERASE
READ
VALID
DQ7
tPLPH
DQ7
30/38
RP
W
tPHQ7V
tPLQ7V
AI02619
A0-A20 ADDRESS (WITHIN BLOCKS) tAVQV tELQV
E tEHQ7V
Figure 10. Data Polling DQ7 AC Waveforms
G tGLQV
W tWHQ7V DQ7 VALID
DQ7
DQ0-DQ6/ DQ8-DQ15
IGNORE tQ7VQV
VALID
M59DR032A, M59DR032B
LAST WRITE CYCLE OF PROGRAM OR ERASE INSTRUCTION
DATA POLLING READ CYCLES
DATA POLLING (LAST) CYCLE
MEMORY ARRAY READ CYCLE
AI02625
31/38
32/38
VALID tEHQV tAVQV tELQV tGLQV tWHQV STOP TOGGLE VALID IGNORE VALID DATA TOGGLE READ CYCLE DATA TOGGLE READ CYCLE MEMORY ARRAY READ CYCLE
AI02543
M59DR032A, M59DR032B
A0-A20
E
Figure 11. Data Toggle DQ6, DQ2 AC Waveforms
G
W
DQ6,DQ2
DQ0-DQ1,DQ3-DQ5, DQ7-DQ15
LAST WRITE CYCLE OF PROGRAM OF ERASE INSTRUCTION
Note: All other timings are as a normal Read cycle.
M59DR032A, M59DR032B
Figure 12. Data Polling Flowchart Figure 13. Data Toggle Flowchart
START
START
READ DQ5 & DQ7 at VALID ADDRESS
READ DQ5 & DQ6
DQ7 = DATA NO NO
YES
DQ6 = TOGGLES YES NO
NO
DQ5 =1 YES READ DQ7
DQ5 =1 YES READ DQ6
DQ7 = DATA NO FAIL
YES
DQ6 = TOGGLES YES PASS FAIL
NO
PASS
AI02574 AI02626
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M59DR032A, M59DR032B
Table 29. Ordering Information Scheme
Example: Device Type M59 Architecture D = Dual Bank Page Mode Operating Voltage R = 1.8V Device Function 032A = 32 Mbit (2Mb x16), Dual Bank: 1/8-7/8 partitioning, Top Boot 032B = 32 Mbit (2Mb x16), Dual Bank: 1/8-7/8 partitioning, Bottom Boot 032C = 32 Mbit (2Mb x16), Dual Bank: 1/4-3/4 partitioning, Top Boot 032D = 32 Mbit (2Mb x16), Dual Bank: 1/4-3/4 partitioning, Bottom Boot 032E = 32 Mbit (2Mb x16), Dual Bank: 1/half-1/half partitioning, Top Boot 032F = 32 Mbit (2Mb x16), Dual Bank: 1/half-1/half partitioning, Bottom Boot Random Speed 100 = 100 ns 120 = 120 ns Package N = TSOP48: 12 x 20mm ZB = FBGA48: 0.75mm pitch Temperature Range 1 = 0 to 70C 6 = -40 to 85C Option T = Tape & Reel packing M59DR032A 100 ZB 6 T
Devices are shipped from the factory with the memory content erased (to FFFFh). For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
Table 30. Revision History
Date May 1999 09/03/99 10/20/99 First Issue FBGA Package Outline drawing change FBGA Connections change (Table 1, Figure 2A) tWHGL and tEHGL Specification change (Table 26, 27) Daisy Chain diagrams, Package and PCB Connections, added (Figure 16, 17) Revision Details
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M59DR032A, M59DR032B
Table 31. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data
mm Symbol Typ A A1 A2 B C D D1 E e L N CP 0.50 0.05 0.95 0.17 0.10 19.80 18.30 11.90 - 0.50 0 48 0.10 Min Max 1.20 0.15 1.05 0.27 0.21 20.20 18.50 12.10 - 0.70 5 0.020 0.002 0.037 0.007 0.004 0.780 0.720 0.469 - 0.020 0 48 0.004 Typ Min Max 0.047 0.006 0.041 0.011 0.008 0.795 0.728 0.476 - 0.028 5 inches
Figure 14. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Drawing is not to scale.
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M59DR032A, M59DR032B
Table 32. FBGA48 - 8 x 6 balls, 0.75 mm pitch, Package Mechanical Data
mm Symbol Typ A A1 A2 b ddd D D1 e E E1 SD SE 7.000 5.250 0.750 12.000 3.750 0.375 0.375 6.800 - - 11.800 - - - 1.250 0.300 0.700 0.450 0.400 0.550 0.075 7.200 - - 12.200 - - - 0.276 0.207 0.030 0.472 0.148 0.015 0.015 0.268 - - 0.465 - - - 0.250 0.350 Min Max Typ 0.492 0.012 0.275 0.018 0.016 0.022 0.003 0.283 - - 0.480 - - - 0.010 0.014 Min Max inches
Figure 15. FBGA48 - 8 x 6 balls, 0.75 mm pitch, Package Outline
D D1 SD BALL "A1"
E
E1
SE
ddd
e A
b A2 A1
BGA-Z03
Drawing is not to scale.
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M59DR032A, M59DR032B
Figure 16. Daisy Chain - Package Connections (Top View)
1 2 3 4 5 6 7 8
A
B
C
D
E
F
AI03079
Figure 17. Daisy Chain - PCB Connections (Top View)
1 2 3 4 5 6 7 8 START
A
B
C
D
E
F
STOP
AI3080
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M59DR032A, M59DR032B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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